Industry standards have been widely relied upon in the design and manufacture of a number of computer system components and functions. One particular example is computer bus architectures. Generally speaking, computer bus architectures are concerned with the interface and communication between processing, memory and input/output computer system components. One commonly-used bus interface is defined as “Peripheral Component Interconnect” (PCI). At the time it was developed, PCI was a very advanced, high-performance parallel bus standard. More recently, a newer bus standard has been developed to more fully utilize new communication technologies (e.g., packet-based, point-to-point communication). This standard is referred to as “PCI Express”.
This newer PCI Express standard defines the auxiliary power (Vaux) to be at the same voltage level as the primary power supply. That is, the auxiliary power is defined as 3.3 Vaux, with the primary supply being +3.3V. The use of the same voltage levels makes it significantly more difficult to design a seamless Vaux switch mechanism for the PCI Express standard. In the prior PCI standard (PCI 2.2 in particular), the primary supply was maintained at a voltage level of 5.0 volts, with Vaux at 3.3 volts. There exists a variety of commercially-available products capable of providing relatively seamless switching between these two different power supplies. The ability to “seamlessly” switch (i.e., abruptly switching sources without any interruption in supplied voltage) to and from Vaux is an important capability for PCI Express add-in cards.
Prior art arrangements that are intended for the older PCI 2.2 standard typically add more circuitry, complexity and cost to the power supply by performing the primary/Vaux power supply switching as a stand-alone function on the power input lines. Moreover, existing prior art devices do not allow a voltage offset for the switch between the primary and Vaux power supplies while operating both rails at 3.3 volts. Such an offset is highly desirable in the PCI Express environment to ensure that the plug-in card operates on the correct supply at all times, even if the supplies are at the far limits of their respective tolerance ranges.